The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having a vertical gate and a method for fabricating the semiconductor device.
Recently, a memory device of sub-40 nm is required to enhance a degree of integration. However, it is rather difficult to achieve the memory device of sub-40 nm in case a transistor has a planar channel or a recess channel that is used in an 8F2 or 6F2 cell architecture, wherein F represents a minimum feature size. Therefore, there is required a dynamic random access memory (DRAM) device having a 4F2 cell architecture capable of enhancing the degree of integration 1.5 to 2 times in the same scaling. As a result, a semiconductor device having a vertical gate is proposed.
The semiconductor device having the vertical gate includes a pillar type active region, i.e., an active pillar, and a surround type vertical gate surrounding the active pillar by processing a semiconductor substrate, wherein a transistor includes the surround type vertical gate and a channel vertically formed on and below the active pillar around the vertical gate.
To fabricate the semiconductor device having the vertical gate, a buried bit line BBL is formed through the ion implantation and a trench process is performed to separate neighboring buried bit lines from each other.
FIG. 1 illustrates a cross-sectional view of a method for fabricating a semiconductor device having a conventional vertical gate.
Referring to FIG. 1, an active pillar 12 having a recessed sidewall is formed by etching a substrate 11 using a protection layer 13 as an etch barrier. A gate dielectric layer 17 is formed on the recessed sidewall of the active pillar 12 and then a vertical gate 14 surrounding the recessed sidewall of the active pillar 12 is formed on the gate dielectric layer 17.
Subsequently, after forming an impurity region in the substrate 11 through the ion implantation, the impurity region is divided by forming a trench 16 that reaches a depth where the impurity region is divided. Herein, the divided impurity regions become buried bit lines 15A and 15B.
However, the prior art has the following problems which will be described in relation to FIGS. 2A to 2C.
FIGS. 2A to 2C show the problems according to the prior art.
First of all, an isotropic etching process is performed to form a recessed sidewall of an active pillar. At this point, since a size of a lower portion of the active pillar is smaller than that of an upper portion thereof, pillar collapse may occur as can be seen from a reference numeral A of FIG. 2A.
Referring to FIG. 2B, an upper portion of an active pillar is damaged as performing an oxide etch-back process to form a buried bit line and prevent the leakage.
Referring to FIG. 2C, an upper portion of an active pillar is damaged when performing an etch-back process to form a vertical gate.